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71311hkpc 018-11-0003/61610hkpc no.a1733-1/26 http://onsemi.com semiconductor components industries, llc, 2013 june, 2013 STK672-432B-E overview the STK672-432B-E is a hybrid ic for use as a unipolar, 2-phase stepping motor driver with pwm current control. applications ? office photocopiers, printers, etc. features ? built-in motor terminal open detection function (output current off). ? built-in overcurrent detection function (output current off). ? built-in overheat detection function (output current off). ? fault1 signal (active low) is output when any of moto r terminal open, overcurrent, or overheat is detected. the fault2 signal is used to output the result of activation of protection circuit detection at 3 levels. ? built-in power on reset function. ? a micro-step sine wave-driven driver can be ac tivated merely by inputting an external clock. ? external pins can be used to select 2, 1-2 (including pseudo-micro), w1-2, 2 w1-2, or 4w1-2 excitation. ? the switch timing of the 4-phase distributor can be switched by setting an external pin (mode3) to detect either the rise and fall, or rise only, of clock input. ? phase is maintained even when th e excitation mode is switched. rotational direction switching function. ? supports schmitt input for 2.5v high level input. ? incorporating a current detection resistor (0.152 : resistor tolerance 2%), motor current can be set using two external resistors. ? the enable pin can be used to cut output current while maintaining the excitation mode. ? with a wide current setting range, power consumption can be reduced during standby. ? no motor sound is generated during hold mode due to external excitation current control. ordering number : ena1733a thick-film hybrid ic 2-phase stepping motor driver
STK672-432B-E no.a1733-2/26 specifications absolute maximum ratings at tc = 25 c parameter symbol conditions ratings unit maximum supply voltage 1 v cc max no signal 50 v maximum supply voltage 2 v dd max no signal -0.3 to +6.0 v input voltage v in max logic input pins -0.3 to +6.0 v output current 1 i op max 10 s, 1 pulse (resistance load) 10 a output current 2 i oh max v dd =5v, clock 200hz 2.5 a allowable power dissipation 1 pdmf max with an arbitrarily large heat sink. per mosfet 7.3 w allowable power dissipation 2 pdpk max no heat sink 2.8 w operating substrate temperature tc max metal surface temperature of the package -20 to +105 c junction temperature tj max 150 c storage temperature tstg -40 to +125 c allowable operating ranges at ta=25 c parameter symbol conditions ratings unit operating supply voltage 1 v cc with signals applied 0 to 46 v operating supply voltage 2 v dd with signals applied 5 5% v input high voltage v ih pins 10, 11, 12, 13, 14, 15, 17, v dd =5 5% 2.5 to v dd v input low voltage v il pins 10, 11, 12, 13, 14, 15, 17, v dd =5 5% 0 to 0.8 v output current i oh tc=105 c, clock 200hz 2.0 a clock frequency f cl minimum pulse width: at least 10 s 0 to 50 khz recommended vref range vref 0.14 to 1.48 v electrical characteristics at tc=25 c, v cc =24v, v dd =5.0v *1 parameter symbol conditions min typ max unit v dd supply current i cco v dd =5.0v, enable=low 5.7 7.0 ma output average current *2 ioave r/l=1 /0.62mh in each pha se 0.19 0.23 0.27 a fet diode forward voltage vdf if=1a (r l =23 ) 1 1.6 v output saturation voltage vsat r l =23 0.35 0.50 v v ih pins 10, 11, 12, 13, 14, 15, 17 2.5 v dd v input voltage v il pins 10, 11, 12, 13, 14, 15, 17 -0.3 0.8 v 5v level input current i ilh pins 10, 11, 12, 13, 14, 15, 17=5v 50 75 a control input pin gnd level input current i ill pins 10, 11, 12, 13, 14, 15, 17=gnd 10 a vref input bias current i ib pin 19 =1.0v 1 a output low voltage v olf pin 16 (i o =5ma) 0.25 0.5 v fault1 pin 5v level leakage current i ilf pin 16 =5v 10 a motor terminal open detection output voltage v of 1 0.0 0.01 0.2 overcurrent detection output voltage v of 2 2.4 2.5 2.6 fault2 pin overheat detection output voltage v of 3 pin 8 (when all protection functions have been activated) 3.1 3.3 3.5 v overheat detection temperature tsd design guarantee 144 c pwm frequency fc 41 48 55 khz drain-source cut-off current i dss v ds =100v, pins 2, 6, 9, 18=gnd 1 a notes *1: a fixed-voltage power supply must be used. *2: the value for ioave assumes that the lead frame of the product is soldered to the mounting circuit board. continued on next page. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
STK672-432B-E no.a1733-3/26 continued from preceding page. parameter symbol conditions min typ max unit 4w1-2 2w1-2 w1-2 1-2 =15/16, 16/16 100 4w1-2 2w1-2 =14/16 97 4w1-2 =13/16 95 4w1-2 2w1-2 w1-2 =12/16 93 4w1-2 =11/16 87 4w1-2 2w1-2 =10/16 83 4w1-2 =9/16 77 4w1-2 2w1-2 w1-2 1-2 =8/16 71 4w1-2 =7/16 64 4w1-2 2w1-2 =6/16 55 4w1-2 =5/16 47 4w1-2 2w1-2 w1-2 =4/16 40 4w1-2 =3/16 30 4w1-2 2w1-2 =2/16 20 4w1-2 =1/16 11 a ? b chopper current ratio 2 vref *3 100 % notes *3: the values given for vref are design targets, no measurement is performed. package dimensions unit:mm (typ) (11.0) (3.5) 11.0 14.4 18 1.0=18.0 4.5 0.4 2.0 4.0 24.2 (r1.47) (18.4) 119 14.4 0.5 1.0 4.45
STK672-432B-E no.a1733-4/26 derating curve of motor current, i oh, vs. STK672-432B-E operating substrate temperature, tc notes ? the current range given above represents conditions wh en output voltage is not in the avalanche state. ? if the output voltage is in the avalan che state, see the allowable avalanche en ergy for stk672-4** series hybrid ics given in a separate document. ? the operating substrate temperature, tc, given abov e is measured while the motor is operating. because tc varies depending on the am bient temperature, ta, the value of i oh , and the continuous or intermittent operation of i oh , always verify this value using an actual set. ? the tc temperature should be checked in the cent er of the metal surface of the product package. 3.0 0.5 0 080 20 40 60 100 70 10 30 50 90 110 itf02592 2.0 2.5 1.5 1.0 i oh - tc operating substrate temperature, tc- c motor current, i oh - a 200hz 2 phase excitation hold mode
STK672-432B-E no.a1733-5/26 block diagram sample application circuit 2-phase stepping motor moi s.g fault1 fault2 cwb enable resetb clock v dd =5v r01 17 11 10 12 9 13 15 14 7 19 4 5 3 1 a ab b bb p.g2 p.g1 2 6 18 16 8 + + c01 at least 100 f c02 10 f v cc =24 v p.gnd vref r02 STK672-432B-E enable 15 fault1 16 p.g1 6 p.g2 1 4.9 2 s.g 18 mode1 10 v dd v ss 9 moi 7 fault2 8 vref sub f1 f2 f3 f4 19 a 4 ab 5 b 3 bb 1 mode2 11 cwb 13 clock 12 mode3 17 resetb 14 excitation mode selection phase excitation signal generator phase advance counter current divider ratio switching pseudo sine wave generator rising edge / falling edge detection power-on reset overheating detection overcurrent detection oscillator reference clock generator pwm control latch open detection
STK672-432B-E no.a1733-6/26 precautions [gnd wiring] ? to reduce noise on the 5v/24v system, be sure to place the gnd of c01 in the circu it given above as close as possible to pin 2 and pin 6 of the hybrid ic. in addition, in order to set the current accurately, the gnd side of ro2 of vref must be connected to the shared ground terminal used by the pin 18 (s.g) gnd, p.g1 and p.g2. [input pins] ? if v dd is being applied, use care that each input pin does not apply a negative voltage less than -0.3v to s.gnd, pin 18. measures must also be taken so that a voltage equal to or greater than v dd is not input. ? high voltage input other than v dd , moi, fault1, and fault2 is 2.5v. ? pull-up resistors are not connected to input pins. pull-down resistors are attached. when controlling the input to the hybrid ic with the open collector type, be sure to connect a pull-up resistor (1 to 20k ). be sure to use a device (0.8v or less, low level, when i ol =5ma) for the open co llector driver at this time that has an output voltage specification such that voltage is pulled to less than 0.8v at low level. ? when using the power on reset function built into the h ybrid ic, be sure to directly connect pin 14 to v dd . ? we recommend attaching a 1,000pf cap acitor to each input to prevent malfunction during high-impedance input. be sure to connect the cap acitor near the hybrid ic, between pin 18 (s, g). when input is fixed low, directly connect to pin 18. when input is fixed high, directly connect to v dd . [current setting vref] if the motor current is temporarily reduced, the circuit given below is recommended. the variable voltage range of vref input is 0.14 to 1.48v. [setting the motor current] the motor current, i oh , is set using the pin 19 voltage, vref, of the hybrid ic. equations related to i oh and vref are given below. vref (ro2 (ro2+ro1)) v dd (5v) (1) i oh (vref 4.9) rs (2) the value of 4.9 in equation (2) above represents the vref voltage as divided by a circuit inside the control ic. rs: 0.152 (current detection resistor inside the hybrid ic) 5v ro1 ro2 r3 5v ro1 ro2 r3 vref vref
STK672-432B-E no.a1733-7/26 ? motor current peak value i oh setting [smoke emission precuations] if pin 18 (s.g terminal) is attached to the pcb without using solder, overcurrent may flow into the mosfet at v cc on (24v on), to emit smoke because 5v circuits cannot be controlled. function table m2 0 0 1 1 m1 m3 0 1 0 1 clock edge timing for phase switching 1 2-phase excitation selection 1-2-phase excitation (i oh =100%) w1-2 phase excitation 2w1-2 phase excitation clock rising edge 0 1-2 phase excitation (i oh =100%, 71%) w1-2 phase excitation 2w1-2 phase excitation 4w1-2 phase excitation clock both edges i oh =100% results in the vref voltage setting, i oh . during 1-2 phase excitation, the hybrid ic operates at a current setting of i oh =100% when the clock signal rises. conversely, pseudo micro cu rrent control is performed to control current at i oh =100% or 71% at both edges of the clock signal. cwb pin forward/cw 0 reverse/ccw 1 enable ? resetb pin enable motor current cut: low resetb active low i oh 0
STK672-432B-E no.a1733-8/26 timing charts 2-phase excitation timing charts (m3=1) 1-2-phase excitation timing charts (m3=1) w1-2-phase excitation timing charts (m3=1) 2w1-2-phase excitation timing charts (m3=1) m1 m2 m3 reset cwb clk a b a 0 0 100% 71% 100% 71% vref vref 0 1 a phase b moi comparator reference voltage mosfet gate signal m1 m2 m3 reset cwb clk a b a 0 0 100% 71% 40% 100% 92% 92% 71% 40% vref vref 0 1 1 b moi comparator reference voltage mosfet gate signal m1 m2 m3 reset cwb clk a b a 0 1 0 100% 71% 100% 71% vref vref 0 1 a phase b phase b phase a phase a phase b phase b phase b moi comparator reference voltage mosfet gate signal m1 m2 m3 reset cwb clk a b a 0 0 100% 92% 83% 97% 71% 55% 40% 20% vref 0 1 1 1 100% 92% 83% 97% 71% 55% 40% 20% vref b moi comparator reference voltage mosfet gate signal itf02581 itf02580 itf02583 itf02582
STK672-432B-E no.a1733-9/26 1-2-phase excitation timing charts (m3=0) w1-2-phase excitation timing charts (m3=0) 2w1-2-phase excitation timing charts (m3=0) 4w1-2-phase excitation timing charts (m3=0) a phase a phase b phase b phase a phase a phase b phase b phase m1 m2 m3 reset cwb clk a b a 0 0 100% 71% 100% 71% vref vref 0 b moi comparator reference voltage mosfet gate signal m1 m2 m3 reset cwb clk a b a 0 0 1 100% 92% 71% 40% 92% 40% 100% 71% vref vref 0 b moi comparator reference voltage mosfet gate signal itf02585 itf02584 m1 m2 m3 reset cwb clk a b a 0 0 1 100% 92% 83% 97% 71% 55% 40% 20% vref 0 100% 92% 83% 97% 71% 55% 40% 20% vref b moi comparator reference voltage mosfet gate signal itf02586 m1 m2 m3 reset cwb clk a b a 0 0 1 1 100% 95% 88% 77% 64% 97% 92% 83% 71% 55% 47% 40% 30% 20% 11% vref 0 b moi comparator reference voltage mosfet gate signal itf02587 100% 95% 88% 77% 64% 97% 92% 83% 71% 55% 47% 40% 30% 20% 11% vref
STK672-432B-E no.a1733-10/26 usage notes 1. i/o pins and functions of the control block [pin description] hic pin pin name function 7 moi output pin for the excitation monitor 19 vref current value setting 10 mode1 11 mode2 17 mode3 excitation mode selection 12 clock external clock (motor rotation instruction) 13 cwb sets the direction of rotation of the motor axis 14 resetb system reset 15 enable motor current off 16 fault1 8 fault2 motor terminal open/overcurrent/over-heat detection output description of each pin [clock (phase switching clock)] input frequency: dc-20khz (when using both edges) or dc-50khz (when using one edge) minimum pulse width: 20 s (when using both edges) or 10 s (when using one edge) pulse width duty: 40% to 50% both edge, single edge operation m3:1 the excitation phase moves one step at a time at the rising edge of the clock pulse. m3:0 the excitation phase moves alternately one step at a time at the rising and falling edges of the clock pulse. [cwb (motor direction setting)] when cwb=0: the motor rotates in the clockwise direction. when cwb=1: the motor rotates in the counterclockwise direction. do not allow cwb input to vary during the 7 s interval before and after the rising and falling edges of clock input. [enable (forcible off control of excita tion drive output a, ab, b, and bb, and selecting operation/hold status inside the hic)] enable=1: normal operation when enable=0: motor current goes off, and exc itation drive output is forcibly turned off. the system clock inside the hic stops at this time, with no effect on the hic even if input pins other than reset input vary. in addition, since current does not fl ow to the motor, the motor shaft becomes free. if the clock signal used for motor rotation suddenly stops, the motor shaft may advance beyond the control position due to inertia. a slow down setting where the clock cycle gr adually decreases is required in order to stop at the control position. [mode1, mode2, and mode3 (selecting the excitation mode, and selecting one edge or both edges of the clock)] excitation select mode terminal (see the sample application circuit for excitation mode selection), selecting the clock input edge(s). mode setting active timing do not change the mode within 7 s of the input rising or falling edge of the clock signal. [resetb (system-wide reset)] the reset signal is formed by th e power-on reset function built into the hic and the resetb terminal. when activating the internal circuits of the hic using the pow er-on reset signal within the hic, be sure to connect pin 14 of the hic to v dd .
STK672-432B-E no.a1733-11/26 [vref (voltage setting to be used for the current setting reference)] ? pin type: analog input configuration input voltage is in the voltage range of 0.14v to 1.48v. [input timing] the control ic of the driver is equipped with a power on reset function capable of initializing internal ic operations when power is supplied. a 4v typ settin g is used for power on reset. because the specification for the mosfet gate voltage is 5v 5%, conduction of current to output at the time of power on reset adds electromotive stress to the mosfet due to lack of gate voltage. to prevent electromotive stress, be sure to set enable=low while v dd , which is outside the operating supply voltage, is less than 4.75v. in addition, if the resetb terminal is used to in itialize output timing, be sure to allow at least 10 s until clock input. enable, clock, and res etb signals input timing [configuration of control block i/o pins] cwb, enable, and resetb input pins> the input pins of this driver all use schmitt input. typical specifications at tc=25 c are given below. hysteresis voltage is 0.3v (viha-vila). 4vtyp 3.8vtyp at least 10 100k 5v overcurrent thermal shutdown 50k 50k output pin pin 8 50k motor terminal open
STK672-432B-E no.a1733-12/26 input voltage specifications are as follows. v ih =2.5vmin v il =0.8vmax fault1 output ? fault1 is an open drain output. it outputs low level when any of motor terminal open, overcurrent, or overheat is detected. fault2 output output is resistance divided (3 levels) and the type of abnormality detected is converted to the corresponding output voltage. ? motor terminal open: 10mv (typ) ? overcurrent: 2.5v (typ) ? overheat: 3.3v (typ) abnormality detection can be released by a resetb operation or turning v dd voltage on/off. [moi output] the output frequency of this excitation monitor pin varies depending on the excitation mode. for output operations, see the timing chart. vref/4.9 v ss amplifier - + input pin pin 19 output pin pin 16 5v v ss overcurrent motor terminal open overheating
STK672-432B-E no.a1733-13/26 2. STK672-432B-E/442b-e/440b-e overcurrent detection, overheat detection, and motor terminal open detection functions each detection function operates using a latch system and turns output off. because a reset signal is required to restore output operations, once the power supply, v dd , is turned off, you must either again apply power on reset with v dd on or apply a resetb=high low high signal. [motor terminal open detection] this hybrid ic is equipped with a function for detecting open output terminals to prevent thermal destruction of the mosfet due to repeated avalanche operation that occurs when an output terminal connected to the motor is open. the open condition is determined by checking the presence or absence of the flyback curr ent that flows in the motor inductance during the off period of the pwm cycle. detection is performed by using the fact that the flyback current does not flow when a motor terminal is open. when the current level drops, the difference with the gnd potential decreases, making detection difficult. the motor current that can be detected by motor terminal open detection is 1.1a or more with the STK672-432B-E and 1.4a or more with the stk672-442b-e/440b-e. when enable changes from low to high and the stk672-4xxb-e performs constant-current pwm operation that flows a negative current during the 30 s period after the high edge, open detection may activate and stop the driver. the motor current setting voltage vref must be set so th at pwm operation is not performed within a period of 30 s after the high edge. if the motor current setup voltage is set for the rated moto r current, pwm operation is not performed during this 30 s period after the high edge, so this is not a problem. in addition, there is no problem with operation that lowers the current setting vref after the motor rated current is reached as shown in the diagram on the following page. whether constant-current pwm operation is performed during the 30 s period after the high edge can be judged by substituting the motor l and r values into the formula on the following page. vref= (r02 (r01+r02)) 5v (or 3.3v) i oh 1= (vref4.9) rs i oh 1: motor current value to be set i oh 2= (v cc r) (1-e -tr/l ) i oh 2: current value 30 s after the enable high edge ? judgment standard: i oh 1 > i oh 2 r01, r02, 5v (or 3.3v): see the sample application circuit documents. rs: current detection resistance value ( ) v cc : motor supply voltage (v) r: motor winding resistance ( ) l: motor winding inductance (h) ? there is no problem if the i oh 2 obtained by substituting t = 30 s and the motor l and r values is smaller than the current setting value i oh 1. used to set the motor current used for open detection (negative current does not flow when the terminal is open.) current detection resistor voltage 0v (gnd potential) mosfet gate signal terminal open pwm period
STK672-432B-E no.a1733-14/26 capacitors must not be connected between the phase a (pin 4), phase ab (pin 5), phase b (pin 3) and phase bb (pin 1) outputs and gnd. what happens if capacitors are connected is that open-circuit detection may be triggered by the discharge current of the capacitors when the intern al mosfet is set on. this current is not an inductance current generated by the motor winding but a capacitor current so a negative current will not flow to the other phase in each pair of phases, possibly cau sing the driver to shut down. if, when the motor current rises prior to the pwm opera tion, a spike-shaped current exceeding the vref-setting current is generated by excessive external noise, for instan ce, before the current level (1.1a for the STK672-432B-E, 1.4a for the stk672-442b-e and 440b-e motor drivers) at which motor pin open-circuiting can be detected is reached, the internal mosfet is set off. since the mosfet has been set off before the actual motor current reaches 1.1a (or 1.4a ), the level of the negative current subsequently flowing to the other phase in each pair of phases is low, and it may be judged that no negative curren t is flowing, possibly causing open-circuit detection to be triggered. during normal constant-current pwm operation, the duration of 1.25 s, which is equivalent to 6% of the initial operation in the pwm period, corresponds to the section wher e the current is not detected, and this ensures that no current is detected for the linking part of the current that is generated in this section. the no-current detection section is not synchronized at the current rise prior to the pwm operation so when a sp ike-shaped current exceeding the vref-setting current is generated, the mosfet is se t off at the stage where the level of the actual motor current is low. as a result, the level of the negative current subsequently flowing to the other phase in each pair of phases is low, and it may be judged that no negative curren t is flowing, possibly causing open-circuit detection to be triggered. motor current pwm period no-current detection time (1.25
STK672-432B-E no.a1733-15/26 [overcurrent detection] this hybrid ic is equipped with a function for detecting over current that arises when the motor burns out or when there is a short between the motor terminals. overcurrent detection occurs at 3.4a typ with the STK672-432B-E, and 5.0a typ with the stk672-442b-e/440b-e. overcurrent detection begins after an interval of no detection (a dead time of 1.25 s typ) during the initial ringing part during pwm operations. the no detection interval is a peri od of time where overcurrent is not detected even if the current exceeds i oh . [overheat detection] rather than directly detecting the temperature of the semi conductor device, overheat dete ction detects the temperature of the aluminum substrate (144 c typ). within the allowed operating range reco mmended in the specification manual, if a heat sink attached for the purpose of reducing the operating substrate temp erature, tc, comes loose, the semic onductor can operate without breaking. however, we cannot guarantee operations without breaking in the case of operations other than those recommended, such as operations at a current exceeding i oh max that occurs before over current detectio n is activated. 1.25 s typ) mosfet all off overcurrent detection operation when motor pins are shorted current when motor terminals are shorted
STK672-432B-E no.a1733-16/26 3. STK672-432B-E allowabl e avalanche energy value (1) allowable range in avalanche mode when driving a 2-phase stepping motor with constant current chopping using an stk672-4** series hybrid ic, the waveforms shown in figure 1 belo w result for the output current, i d , and voltage, v ds . figure 1 output current, i d , and voltage, v ds , waveforms 1 of the stk672-4** series when driving a 2- phase stepping motor with constant current chopping when operations of the mosfet built into stk672-4** seri es ics is turned off for constant current chopping, the i d signal falls like the waveform shown in the figure above. at this time, the output voltage, v ds , suddenly rises due to electromagnetic induction generated by the motor coil. in the case of voltage that rises suddenly , voltage is restricted by the mosfet v dss . voltage restriction by v dss results in a mosfet avalanche. during avalanche operations, i d flows and the instantaneous energy at this time, eavl1, is represented by equation (3-1). eavl1=v dss iavl 0.5 tavl ------------------------------------------- (3-1) v dss : v units, iavl: a units, tavl: sec units the coefficient 0.5 in equation (3-1) is a constant required to convert the iavl triangle wave to a square wave. during stk672-4** series operations, the waveforms in the figure above repeat due to the constant current chopping operation. the allowable avalanche energy, eavl, is therefore represented by equation (3-2) used to find the average power loss, pavl, during avalanche mode multiplied by the chopping frequency in equation (3-1). pavl=v dss iavl 0.5 tavl fc ------------------------------------------- (3-2) fc: hz units (fc is set to the pwm frequency of 50khz.) for v dss , iavl, and tavl, be sure to actually operate th e stk672-4** series and substitute values when operations are observed using an oscilloscope. ex. if v dss =110v, iavl=1a, tavl=0.2 s when using a STK672-432B-E driver, the result is: pavl=110 1 0.5 0.2 10 -6 50 10 3 =0.55w v dss =110v is a value actually measured using an oscilloscope. the allowable loss range for the allowable avalanche ener gy value, pavl, is shown in the graph in figure 3. when examining the avalanche energy, be sure to actually drive a motor and observe the i d , v dss , and tavl waveforms during operation, and then check that the result of calculating equation (3-2) falls within the allowable range for avalanche operations. v dss : voltage during avalanche operations i oh : motor current peak value iavl: current during avalanche operations tavl: time of avalanche operations v ds i d itf02557
STK672-432B-E no.a1733-17/26 (2) i d and v dss operating waveforms in non-avalanche mode although the waveforms during avalanche mode are given in figure 1, sometimes an avalanche does not result during actual operations. factors causing avalanche are listed below. ? poor coupling of the motor?s phase coils (electromagnetic coupling of a phase and ab phase, b phase and bb phase). ? increase in the lead inductance of the harness caused by the circuit pattern of the p.c. board and motor. ? increases in v dss , tavl, and iavl in figure 1 due to an increase in the supply voltage from 24v to 36v. if the factors above are negligible, the waveforms shown in figure 1 become waveforms without avalanche as shown in figure 2. under operations shown in figure 2, avalanche does not occur and there is no need to consider the allowable loss range of pavl shown in figure 3. figure 2 output current, i d , and voltage, v ds , waveforms 2 of the stk672-4** series when driving a 2-phase stepping motor with constant current chopping figure 3 allowable loss range, pavl-i oh during STK672-432B-E avalanche operations note: the operating conditions given above represent a loss when driving a 2-phase stepping motor with constant current chopping. because it is possible to apply 2.6w or more at i oh =0a, be sure to avoid using the mosfet body diode that is used to drive the motor as a zener diode. i oh : motor current peak value v ds i d itf02558 pavl - i oh motor current,i oh - a 0 0.5 1.0 1.5 2.5 2.0 0.5 0 itf02593 4.0 3.5 2.5 3.0 2.0 1.5 1.0 t c =8 0 c 1 0 5 c average power loss in the avalanche state, pavl- w
STK672-432B-E no.a1733-18/26 4. calculating STK672-432B-E hic internal power loss the average internal power loss in each excitation mode of the STK672-432B-E can be ca lculated from the following formulas. *1 [each excitation mode] 2-phase excitation mode 2pdavex= 2 vsat 0.5 clock i oh t2+0.5 clock i oh (vsat t1+vdf t3) --------------------------- (4-1) 1-2 phase excitation mode 1-2pdavex= 2 vsat 0.25 clock i oh t2+0.25 clock i oh (vsat t1+vdf t3) ---------------------- (4-2) w1-2 phase excitation mode w1-2pdavex=0.64[2 vsat 0.125 clock i oh t2+0.125 clock i oh (vsat t1+vdf t3)] ---------- (4-3) 2w1-2 phase excitation mode 2w1-2pdavex=0.64[2 vsat 0.0625 clock i oh t2+0.0625 clock i oh (vsat t1+vdf t3)] ------ (4-4) 4w1-2 phase excitation mode 4w1-2pdavex=0.64[2 vsat 0.0625 clock i oh t2+0.0625 clock i oh (vsat t1+vdf t3)] ------ (4-5) motor hold mode holdpdavex= 2 vsat i oh ---------------------------------------------------------------------------------------------- (4-6) note: 2-phase 100% conductance is assumed in equation (4-6). vsat: combined voltage of ron voltage drop + current detection resistance vdf: combined voltage of the fet body diode + current detection resistance clock: input clock (hic: input frequency at pin 12) t1, t2, and t3 represent the waveforms shown in the figure below. t1: time required for the winding cu rrent to reach the set current (i oh ) t2: time in the constant current control (pwm) region t3: time from end of phase input signal until inverse current regeneration is complete motor com current waveform model t1= (-l/(r+0.35)) ln (1-(((r+0.35)/v cc ) i oh )) --------------------------------------------------------------- (4-7) t3= (-l/r) ln ((v cc +0.35)/(i oh r+v cc +0.35)) -------------------------------------------------------------- (4-8) v cc : motor supply voltage (v) l: motor inductance (h) r: motor winding resistance ( ) i oh : motor set output current crest value (a) i oh 0a t1 t2 t3
STK672-432B-E no.a1733-19/26 fixed current control time, t2, for each excitation mode (1) 2-phase excitation t2 = (2 clock) - (t1 + t3)(4-9) (2) 1-2 phase excitation t2 = (3 clock) - t1(4-10) (3) w1-2 phase excitation t2 = (7 clock) - t1(4-11) (4) 2w1-2 phase excitation (and 4w1-2 phase excitation) t2 = (15 clock) - t1(4-12) for the values of vsat and vdf, be sure to substitute from vsat vs i oh and vdf vs i oh at the setting current value i oh . (see pages to follow) then, determine if a heat sink is necessary by comparing with the tc vs pd graph (see next page) based on the calculated average output loss, hic. for heat sink design, be sure to see STK672-432B-E. the hic average power, pdavex described above, represents loss when not in avalanche mode. to add the loss in avalanche mode, be sure to add pavl (4-13, 14) using the formula (3-2) for average power loss , pavl, for stk672- 4** avalanche mode, described below to pdavex described above. when using this ic without a fin, always check for temp erature increases in the set, because the hic substrate temperature, tc, varies due to e ffects of convection around the hic. [calculating the averag e power loss, pavl, during avalanche mode] the allowable avalanche energy, eavl, during fixed current chopping operation is represented by equation (3-2) used to find the average power loss, pavl, during avalanche mode that is calculated by multiplying equation (3-1) by the chopping frequency. pavl=v dss iavl 0.5 tavl fc (3-2) fc: hz units (input max pwm frequency when using the stk672-4** series.) be sure to actually operate an stk672-4** series and substitute values found when observing operations on an oscilloscope for v dss , iavl, and tavl. the sum of pavl values for each excita tion mode is multiplied by the constant s given below and added to the average internal hic loss equation, except in the case of 2-phase excitation. 1-2 excitation mode and higher: pavl(1)=0.7 pavl (4-13) during 2-phase excitation and motor hold: pavl(1)=1 pavl (4-14)
STK672-432B-E no.a1733-20/26 output saturation voltage, vsat - output current, i oh forward voltage, vdf -output current, i oh substrate temperature rise, tc (no heat sink) - internal average power dissipation, pdav vsat - i oh output current, i oh - a output saturation voltage, vsat - v 0 0.5 1.0 1.5 3.0 2.5 2.0 0.4 0.2 0 itf02594 1.0 0.8 0.6 2 5 c t c = 1 0 5 c vdf- i oh output current, i oh - a forward voltage, vdf - v 0 0.5 1.0 1.5 3.0 2.5 2.0 0.4 0.2 0 itf02595 1.4 1.0 1.2 0.8 0.6 t c = 2 5 c 1 0 5 c tc - p d a v hybrid ic internal average power dissipation, pdav - w substrate temperature rise, c 80 20 10 0 0 1.0 2.0 3.0 0.5 1.5 2.5 itf02717 50 70 60 40 30
STK672-432B-E no.a1733-21/26 5. thermal design [operating range in which a heat sink is not used] use of a heat sink to lower the operating substrate temperat ure of the hic (hybrid ic) is effective in increasing the quality of the hic. the size of heat sink for the hic varies depending on the magnitude of the average power loss, pdav, within the hic. the value of pdav increases as the output current in creases. to calculate pdav, refer to ?calculating internal hic loss for the STK672-432B-E?. calculate the internal hic loss, pdav, assuming repeat operation such as shown in figure 1 below, since conduction during motor rotation and off time both exist during actual motor operations, figure 1 motor current timing t1: motor rotation operation time t2: motor hold operation time t3: motor current off time t2 may be reduced, depending on the application. t0: single repeated motor operating cycle i o 1 and i o 2: motor current peak values due to the structure of motor windings, the phase current is a positive and negative current with a pulse form. note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ. the hybrid ic internal average power dissipation pdav can be cal culated from the following formula. pdav= (t1 p1+t2 p2+t3 0) to ---------------------------- (i) (here, p1 is the pdav for i o 1 and p2 is the pdav for i o 2) if the value calculated using equation (i) is 1.5w or less, and the ambient temperature, ta, is 60 c or less, there is no need to attach a heat sink. refer to figure 2 for operating substrate temperature data when no heat sink is used. [operating range in which a heat sink is used] although a heat sink is attached to lower tc if pdav in creases, the resulting size can be found using the value of c-a in equation (ii) below and the graph depicted in figure 3. c-a= (tc max-ta) pdav ---------------------------- (ii) tc max: maximum operating substrate temperature =105 c ta: hic ambient temperature although a heat sink can be designed based on equations (i) and (ii) above, be sure to mount the hic in a set and confirm that the substrate temperature, tc, is 105 c or less. the average hic power loss, pdav, described above represents the power loss when there is no avalanche operation. to add the loss during avalanche operations, be sure to add equation (3-2), ?allo wable stk672-4** avalanche energy value?, to pdav. i o 1 i o 2 -i o 1 0a t1 t2 t3 t0 motor phase current (sink side)
STK672-432B-E no.a1733-22/26 figure 2 substrat e temperature rise, tc - internal average power dissipation, pdav figure 3 heat sink area (board thickness: 2mm) - c-a 2 1.0 2 100 7 10 35 2 7 35 1000 c-a - s heat sink area, s - cm 2 heat sink thermal resistance, c-a - c/w itf02554 5 100 3 10 7 2 5 3 7 w i t h n o s u r f a c e f i n i s h w ith a f la t b la c k s u r f a c e f in is h tc - p d a v hybrid ic internal average power dissipation, pdav - w substrate temperature rise, c 80 20 10 0 0 1.0 2.0 3.0 0.5 1.5 2.5 itf02717 50 70 60 40 30
STK672-432B-E no.a1733-23/26 6. mitigated curve of package power loss, pdpk, vs. ambient temperature, ta package power loss, pdpk, refers to the average internal power loss, pdav, allowable without a heat sink. the figure below represents the allowable power loss, pd pk, vs. fluctuations in the ambient temperature, ta. power loss of up to 2.8w is allowable at ta=25 c, and of up to 1.5w at ta=60 c. * the package thermal resistance c-a is 28.6c/w. allowable power dissipation, pdpk (no heat sink) - ambient temperature, ta pdpk - ta ambient temperature, ta - c allowable power dissipation, pdp k - w 1.0 0.5 0 080 20 40 60 100 120 itf02718 2.5 3.0 2.0 1.5
STK672-432B-E no.a1733-24/26 7. other notes on use in addition to the ?notes? indicated in the sample application circuit, care should also be given to the following contents during use. (1) allowable operating range operation of this product assumes use within the allo wable operating range. if a supply voltage or an input voltage outside the allowable operating range is applied, an overvoltage may damage the internal control ic or the mosfet. if a voltage application mode that exc eeds the allowable operating range is anticipated, connect a fuse or take other measures to cut off power supply to the product. (2) input pins if the input pins are connected directly to the pc board connectors, electrostatic discharge or other overvoltage outside the specified range may be applied from the connectors and may damage the product. current generated by this overvoltage can be suppressed to effectively prevent damage by inserting 100 to 1k resistors in lines connected to the input pins. take measures such as inserting resistors in lines connected to the input pins. (3) power connectors if the motor power supply v cc is applied by mistake without connectin g the gnd part of the power connector when the product is operated, such as for test purposes, an overcurrent flows through the v cc decoupling capacitor, c1, to the parasitic diode between the v dd of the internal control ic and gnd, and may damage the power supply pin block of the internal control ic. to prevent damage in this case, connect a 10 resistor to the v dd pin, or insert a diode between the v cc decoupling capacitor c1 gnd and the v dd pin. (4) input signal lines 1) do not use an ic socket to mount the driver, and instead solder the driver directly to the pc board to minimize fluctuations in the gnd potential due to the influence of the resistance component and inductance component of the gnd pattern wiring. 2) to reduce noise caused by electro magnetic induction to small signal lines, do not design small signal lines (sensor signal lines, and 5v or 3.3v power supply signal lines) that run parallel in close proximity to the motor output line a (pin 4), ab (pin 5), b (pin 3), or bb (pin 1) phases. mode1 fao c1 r1 r2 gnd open fabo fbo fbbo ai bi vref v dd v dd =5v v cc v ss clock cwb resetb enable mode2 mode3 fault1 vref s.g 9 18 4 2 6 a 5 ab 3 b 1 bb overcurrent protection measure: insert a resistor. overcurrent protection measure: insert a diode. over-current path 5v reg. 24v reg.
STK672-432B-E no.a1733-25/26 (5) when mounting multiple drivers on a single pc board when mounting multiple drivers on a single pc board, the gnd design should mount a v cc decoupling capacitor, c1, for each driver to stabili ze the gnd potential of the other drivers. the key wiring points are as follows. (6) v cc operating limit when the output (for example f1) of a 2-phase stepping motor driver is turned off, the ab phase back electromotive force eab produced by current flowing to the paired f2 parasitic diode is induced in the f1 side, causing the output voltage vfb to become twice or more the v cc voltage. this is expressed by the following formula. vfb = v cc + eab = v cc + v cc + i oh x rm + vdf (1.5 v) v cc : motor supply voltage, i oh : motor current set by vref vdf: voltage drop due to f2 parasitic diode and curre nt detection resistor r1, rm: motor winding resistance value using the above formula, make sure that vfb is always less than the mosfet withst and voltage of 100v. this is because there is a possibility that operating limit of v cc falls below the allowable operating range of 46v, due to the rm and i oh specifications. the oscillating voltage in excess of vfb is caused by l crm (inductance, capacitor, re sistor, mutual inductance) oscillation that includes micro capacitors c, not presen t in the circuit. since m is affected by the motor characteristics, there is some differen ce in oscillating voltage according to the motor specifications. in addition, constant voltage drive without constant current drive enables motor rotation at v cc 0v. f1 on f2 off v cc r1 m f1 off f2 off v cc r1 m gnd gnd a p hase ab phase ab p hase a p hase vfb v cc eab current path current path eab eab is generated by the mutual induction m. 5v 9 19 18 2 6 ic1 moto r 1 short thick thick and short gnd 24v gnd 9 19 18 2 6 ic2 moto r 2 9 19 18 2 6 ic3 moto r 3 input input input signals
STK672-432B-E no.a1733-26/26 ps on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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